This invention relates to an improved method for constructing irritator programs from a graphical description useful to verify logic at the logic design level and also, more particularly, to facilitate the construction of stimulation and checker programs to exercise the logic to be tested.
Trademarks: S/390 and IBM are registered trademarks of International Business Machines Corporation, Armonk, N.Y., U.S.A. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies.
The task of verification of a logic design is usually done by examining small pieces of logic (called units) first. Then these pieces are grouped together to form bigger blocks, up to the point where a simulation model contains the whole system. In this way, large systems are debugged and verified bottom-up in a hierarchical manner.
Below system level, state of the art verification methods replace missing hardware components by software, so-called irritator behaviorals (i.e. random simulation driver inputs). They are attached to the interfaces of the logic under test.
This approach to logic design verification are deficient in at least two respects. If the task of verification is the responsibility of the logic designer, the programming language which is used (usually C/C++) is often unfamiliar to him or her.
In any case, programming an irritator program is tedious and error-prone. Given ever increasing design complexity and therefore number of units, increasing numbers of irritators are required. In current designs, a substantial amount of time is necessary to write and debug the irritator programs.
A big improvement has been the introduction of the Timediag/Genrand tools (IBM""s Bruce Wile""s U.S. Pat. No. 5,745,386, entitled xe2x80x9cTiming Diagram Method For Inputting Logic Design Parameters To Build A Testcase For The Logic Diagramxe2x80x9d), which allowed the use of timing diagrams as irritator programs for S/390 designer level efforts for a few designs. Using Timediag, timing diagrams could be constructed easily using a graphical interface. While the improvement was great, the tools created in accordance with this patent were as described for support of designer level simulation, and this was achieved for the lowest level of verification using small designs only (e.g restriction in the number of timing diagrams).
This current invention provides a method for verifying logic designs which uses the concepts of irritator behaviorals but with a timing diagram input format, which can be used intuitively by logic designers without knowledge about the underlying programming language. The preferred embodiment enables the designer user to lay out and/or edit a timing diagram using a Timing Diagram Editor with a TD-compile (Timing Diagram compile which now generates in accordance with this invention an executable timing diagram for the graphical input provided by the user). Instead of manually programming a behavioral description of a logic circuit, the behavior of signals at any given time is specified in a spreadsheet like editor. These spreadsheets then are compiled into an executable irritator program for logic verification. Providing a graphical user interface to specify logic behavior makes testcase generation much easier and more intuitive. This results in significant savings of time.
In accordance with this invention a method is provided to translate a behavioral description of a logic design or an interface protocol, available in timing diagram format, into a C++ class. The C++ file generated then is compiled into a stand-alone executable file or a shared library, whatever the preferences of the user are. Shell scripts are used to control compilation of the C++ file, so the user can modify the way an executable is generated (e.g. with compile optimization, and with debug support and with other user desired modification of generation of compiles).
In accordance with the invention a random driver program is used to read a configuration file containing a list of timing diagrams and other parameters to generate therefrom a random simulation driver.
The invention provides support for multiple clock domains, where different parts of a design under test run at different clock speeds.
These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the detailed description and to the drawings.